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CSS3110: Computer Organization and Architecture II

(ANC-CSS3110.AB1)
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1

Assembly Language, Processor Structure, and Function

  • Assembly Language Concepts
  • Motivation For Assembly Language Programming
  • Assembly Language Elements
  • EXAMPLES
  • Types of assemblers
  • Assemblers
  • Loading and Linking
  • Processor Organization
  • Register Organization
  • Instruction Cycle
  • Instruction Pipelining
  • Processor Organization for Pipelining
  • The x86 Processor Family
  • The ARM Processor
2

Reduced Instruction Set, Instruction-Level Parallelism, and Superscalar Processors

  • Instruction Execution Characteristics
  • The Use of a Large Register File
  • Compiler-Based Register Optimization
  • Reduced Instruction Set Architecture
  • RISC Pipelining
  • MIPS R4000
  • SPARC
  • Processor Organization For Pipelining
  • CISC, RISC, And Contemporary Systems
  • Overview
  • Design Issues
  • Intel Core Microarchitecture
  • ARM Cortex-A8
  • ARM Cortex-M3
3

Control Unit Operation and Microprogrammed Control

  • Micro-Operations
  • Control of the Processor
  • Hardwired Implementation
  • Microprogrammed Control
4

Parallel Processing

  • Multiple Processor Organizations
  • Symmetric Multiprocessors
  • Cache Coherence and the MESI Protocol
  • Multithreading and Chip Multiprocessors
  • Clusters
  • Nonuniform Memory Access
5

Multicore Computers

  • Hardware Performance Issues
  • Software Performance Issues
  • Multicore Organization
  • Heterogeneous Multicore Organization
  • INTEL Core i7-5960X
  • ARM Cortex-A15 MPCore
  • IBM z13 Mainframe

1

Assembly Language, Processor Structure, and Function

  • Using Greatest Common Divisor
2

Reduced Instruction Set, Instruction-Level Parallelism, and Superscalar Processors

  • Determining Characteristics of Processors
3

Control Unit Operation and Microprogrammed Control

  • Understanding The Functioning of Microprogrammed Control Unit
4

Parallel Processing

  • Determing the Types of Parallel Processor Systems
5

Multicore Computers

  • Identifying Levels of Cache

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